Modular data memory systems usually have a system board with a plurality of slots for memory modules. The slots are occupied by memory modules in each case depending on the requirements made of the data memory system or on an expansion level of the data memory system.
One example of a data memory system with a modular concept is a computer system (PC, workstation, server) with variable main memory in which slots for memory modules in the form of plug-in sockets are provided on a system board. The memory modules of modular data memory systems are generally present in the form of DIMMs (dual inline memory modules), whose mechanical and electrical interfaces to the system board are subject to industry standards.
In order to increase the performance of such data memory systems, efforts are generally made to increase a clock or data transfer rate. Thus, data transfer rates of 667 Mbits per second and per data signal (Mbit/s/Pin) are provided for DDRII (double data rate) memory systems based on DDR-DRAM modules (double data rate dynamic random access memories) as data memory devices and data transfer rates of up to 1.5 Gbit/s/Pin are provided for DDRIII memory systems. With rising data transfer rates, measures for preserving or improving the signal integrity at high signal frequencies are increasingly gaining in importance.
Known concepts for data memory systems with data transfer rates of up to 1.5 Gbit/s/Pin provide, on the memory modules, branch-free signal lines and distributed capacitive loads for improving the signal integrity.
Equally, buffer/redriver modules are known, which are in each case provided in addition to the data memory devices on the memory modules. The buffer/redriver modules enable, besides a signal conditioning of signals routed to or from the data memory devices of the memory modules, a decoupling of a bus system embodied on the system board from the bus systems respectively formed on the memory modules.
Furthermore, error correction concepts (ECC, error correction codes) are known for data protection purposes. To that end, a first set of redundant data (redundancy data hereinafter) is transferred in parallel with the actual user data, said first set of redundant data in each case being formed from the user data according to known algorithms. The redundancy data are transferred in addition to the respectively corresponding user data for instance to a further data memory device situated on the memory module and are stored. After the user data and the redundancy data have been transferred back to a memory checking module that is generally arranged on the system board, a second set of redundant data (check data hereinafter) is formed there from the user data. Through the comparison of the check data with the redundancy data that are transferred together with the user data, error events are registered and corrected case by case according to known technology. An error event is present in this case if the user data transferred back to the memory checking module deviate from the user data originally transferred from the memory checking module to one of the data memory devices. An error event is based on a transfer error, a defective memory cell in the data memory device or on a change in the data content of a memory cell brought about by ambient influences.
Error correction concepts generally presuppose that a set of redundancy data is stored in addition to each set of user data on the memory modules. In the case of memory concepts such as SDR (single data rate), DDRI and DDRII, the entire data bus usually has 64 data lines routed parallel for transferring the user data. Customary error correction concepts provide a further eight data lines for parallel transfer of the redundancy data. Accordingly, the size of the memory for the redundancy data (error data memory hereinafter) per memory module amounts to an eighth of the user data memory of the memory module.
A further error correction concept, known as Chipkill™, is directed at the detection and correction of multiple errors—undetectable by means of conventional error correction concepts—on a physical data address of a data memory device. In this case, essentially the data bits assigned to the physical data address are allocated (scattering) to a group of parallel bus systems for which a customary error correction concept acts separately in each case. In the case of a defective addressing line within the data memory device, a usually undetectable or uncorrectable multiple error is converted into a number of generally correctable single errors.
Generally, when combining a plurality of measures or concepts which increase the performance of a data memory system, their advantages cumulate.
However, a combination of an error correction concept with a buffer/redriver concept realized using conventional means also leads to disadvantages. Thus, the high space requirement for the buffer/redriver modules and the error data memory makes it extraordinarily difficult to suitably form signal lines (routing) on memory modules whose dimensions are standardized according to JEDEC (joint electronic device engineering council).
Further disadvantages of simply combining error correction concepts on the one hand, and buffer/redriver concepts, on the other hand, occur with different weighting depending on a data bus width of the data memory devices provided on the memory module.
Since the error data memory is advantageously operated identically to the user data memory, the error data memory is usually provided with the same properties as the user data memory. Therefore, as a rule, the same type of data memory device is provided for the user data memory and the error data memory. If the data memory devices for the user data memory have a data bus width of sixteen data lines, then the data memory device for the error data memory typically also has a data bus width of 16 bits. Since customary error correction concepts only utilize 8 bits, however, a data memory of the order of magnitude of an eighth of the entire memory capacity of the memory module disadvantageously remains unutilized.
Furthermore, for cost reasons, corresponding types of memory modules with and without error correction have an essentially identical layout of the signal lines. The corresponding types of memory modules differ merely in the fact that memory modules with error correction are equipped with an additional data memory device as error data memory. A slot for the error data memory device is formed in the same way on the memory modules without error correction, but remains unpopulated.
If the memory module has data memory devices with a data bus width of 8 bits, then it is necessary to provide on two corresponding types of memory modules with an internal 64-bit data bus, by way of example, eight slots for data memory devices for storing the user data and a further slot for a (error) data memory device for storing the redundancy data, that is to say overall an odd number of slots for data memory devices. In a disadvantageous manner, however, no topology for the embodiment of the signal lines between the buffer/redriver module and the data memory devices then permits a symmetrical configuration of the in total nine slots for data memory devices on the memory module. According to a so-called “double T-branch” topology that is customary nowadays, by way of example, the data bus is routed in two branches, one branch of the data bus being connected to four slots, and the second branch to five slots, for data memory devices. This leads to an asymmetrical formation of the data signal lines and the optimization of the timing of the data signals for the two configurations of the memory module with and without error correction is made more difficult. For the data transfer rates provided for DDRII, it would be necessary to introduce additional waiting cycles for data transfer on the control and address bus. However, this leads to an undesirable limitation of the data transfer rate and thus of the performance of the data memory system.
On memory modules which have data memory devices with a data width of 4 bits in each case, at least eighteen data memory devices are required in order to provide a total data bus width of 72 bits. Of these, two data memory devices are provided for storing the redundant data. Memory modules with data memory devices based on a data bus width of 4 bits are provided for applications which require a high amount of memory. Therefore, for this purpose, the data memory devices are also in each case provided with a maximum number of memory cells. The space requirement of the memory cells in a semiconductor substrate of the data memory devices results in a comparatively large device size of the data memory devices used therefor. In this case, corresponding memory modules whose dimensions are restricted to a maximum size of 1.2 inches×5.25 inches in accordance with the definitive industry standard are also covered virtually completely with data memory devices. The arrangement of additional buffer/redriver modules and of an additional error data memory device is not possible in these cases for space reasons.
The memory module 1 illustrated in FIG. 1 has dimensions of 1.2 inches×5.25 inches in accordance with the JEDEC standard. Eight DRAMs 2 as user data memories and one further DRAM 3 as error data memory are provided on at least one of the two placement surfaces of the memory module 1. The memory module 1 has an array of contact devices 10 as an electrical interface to a system board of a data memory system. From the array of contact devices 10, an external data bus 51 and also an external control and address bus 63 are routed to a buffer/redriver module 4. The buffer/redriver module 4 is respectively connected to the DRAMS 2, 3 via data signal lines 5. An internal control and address bus is routed in two branches 61, 62 in each case between the buffer/redriver module 4 and the DRAMs 2, 3.
An asymmetrical loading results for the two branches 61, 62 of the internal control and address bus, since four DRAMs 2 are connected to the first branch 61 and five DRAMs 2, 3 are connected to the second branch 62. In this case, the timing of the respective slower branch 61, 62 of the internal control and address bus prescribes the timing of the entire memory module 1. The timing in the second branch 62 furthermore depends on whether the DRAM 3 is furnished for error data storage purposes. Furthermore, it can be recognized that a routing of the data signal lines 5 is made considerably more difficult by the high population density of the memory module 1.
FIG. 2 indicates a second possibility for arranging the DRAMs 2, 3 on the memory module 1. The problem of an asymmetrical distribution of the capacitive loads on the internal control and address bus 61, 62 and of a timing dependent on the furnishing of the DRAM 3 provided as an error data memory remains in this case.
Thus, for the reasons mentioned above, in the context of industry standards currently in force, a combination of buffer/redriver concepts with error correction concepts that is desirable in order to increase the performance of data memory systems is possible, if at all, only with drastic cutbacks elsewhere.